We use cookies to improve your experience with our site.

Indexed in:

SCIE, EI, Scopus, INSPEC, DBLP, CSCD, etc.

Submission System
(Author / Reviewer / Editor)
Advanced Search
Volume 31 Issue 1
January  2016
Turn off MathJax
Article Contents
Abstract
References
Related Articles
Mei-Ying Bian, Su-Kyung Yoon, Jeong-Geun Kim, Sangjae Nam, Shin-Dug Kim. A Unified Buffering Management with Set Divisible Cache for PCM Main Memory[J]. Journal of Computer Science and Technology, 2016, 31(1): 137-146. DOI: 10.1007/s11390-016-1617-7
Citation: Mei-Ying Bian, Su-Kyung Yoon, Jeong-Geun Kim, Sangjae Nam, Shin-Dug Kim. A Unified Buffering Management with Set Divisible Cache for PCM Main Memory[J]. Journal of Computer Science and Technology, 2016, 31(1): 137-146. DOI: 10.1007/s11390-016-1617-7
shu

A Unified Buffering Management with Set Divisible Cache for PCM Main Memory

  • Department of Computer Science, Yonsei University, Seoul 120-749, Korea

Funds: This work was supported by an Industry-Academy Joint Research program between Samsung Electronics and Yonsei University.
More Information
  • Author Bio:

    Mei-Ying Bian received her B.S. degree in information and computing science from Jilin Institute of Chemical Technology, Jilin, in 2008. Currently, she is a M.S. candidate at the Department of Computer Science at Yonsei University, Seoul. Her research interests include computer architecture, memory hierarchy, non-volatile memory, and storage system design.

  • Corresponding author:

    Shin-Dug Kim E-mail: sdkim@yonsei.ac.kr

  • Received Date: May 07, 2014
  • Revised Date: May 07, 2014
  • Published Date: January 04, 2016
    Abstract
  • This research proposes a phase-change memory (PCM) based main memory system with an effective combination of a superblock-based adaptive buffering structure and its associated set divisible last-level cache (LLC). To achieve high performance similar to that of dynamic random-access memory (DRAM) based main memory, the superblock-based adaptive buffer (SABU) is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer (SBPB) and an adaptive sub-block reusing buffer (SBRB), and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.
    • FullText(HTML)
    • References (20)
  • [1]
    Kim S, Chandra D, Solihin Y. Fair cache sharing and partitioning in a chip multiprocessor architecture. In Proc. the 13th International Conference on Parallel Architectures and Compilation Techniques, September 2004, pp.111-122.
    [2]
    Choi I S, Jang S I, Oh C H, Weems C C, Kim S D. A dynamic adaptive converter and management for PRAMbased main memory. Microprocessors and Microsystems, 2013, 37(6/7):554-561.
    [3]
    Jang S I, Yoon S K, Park K, Park G H, Kim S D. Data classification management with its interfacing structure for hybrid SLC/MLC PRAM main memory. The Computer Journal, 2014, DOI 10.1093/comjnl/bxu133.
    [4]
    Dhiman G, Ayoub R, Rosing T. PDRAM:A hybrid PRAM and DRAM main memory system. In Proc. the 46th ACM/IEEE Design Automation Conference, July 2009, pp.664-669.
    [5]
    Yoon S K, Bian M Y, Kim S D. An integrated memory-disk system with buffering adapter and non-volatile memory. Design Automation for Embedded Systems, 2014, 17(3/4):609-626.
    [6]
    Qureshi M K, Srinivasan V, Rivers J A. Scalable high performance main memory system using phase-change memory technology. ACM SIGARCH Computer Architecture News, 2009, 37(3):24-33.
    [7]
    Jung K S, Park J W, Weems C C, Kim S D. A superblock based memory adapter using decoupled dual buffers for hiding the access latency of nonvolatile memory. In Proc. the World Congress on Engineering and Computer Science, October 2011, pp.802-807.
    [8]
    Lee B C, Ipek E, Mutlu O, Burger D. Architecting phase change memory as a scalable dram alternative. ACM SIGARCH Computer Architecture News, 2009, 37(3):2- 13.
    [9]
    Joo Y, Park S. A hybrid PRAM and STT-RAM cache architecture for extending the lifetime of PRAM caches. IEEE Computer Architecture Letters, 2013, 12(2):55-58.
    [10]
    Wang Z, Shan S, Cao T, Gu J, Xu Y, Mu S, Xie Y, Jiménez D A. WADE:Write-back-aware dynamic cache management for NVM-based main memory system. ACM Transactions on Architecture and Code Optimization, 2013, 10(4):Article No. 51.
    [11]
    Fedorov V V, Qiu S, Narasimha Reddy A L, Gratz P V. ARI:Adaptive LLC-memory traffic management. ACM Transactions on Architecture and Code Optimization, 2013, 10(4):Article No. 46.
    [12]
    Saito S, Oikawa S. Exploration of non-volatile memory management in the OS kernel. In Proc. the 3rd International Conference on Networking and Computing, December 2012, pp.302-306.
    [13]
    Kim J K, Lee H G, Choi S, Bahng K I. A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems. In Proc. the 8th ACM International Conference on Embedded Software, October 2008, pp.31-40.
    [14]
    Byna S, Chen Y, Sun X H. A taxonomy of data pre-fetching mechanisms. In Proc. International Symposium on Parallel Architectures, Algorithms, and Networks, May 2008, pp.19- 24.
    [15]
    Nesbit K, Smith J E. Data cache pre-fetching using a global history buffer. IEEE Micro, 2005, 25(1):90-97.
    [16]
    Henning J L. SPEC CPU2006 benchmark descriptions. ACM SIGARCH Computer Architecture News, 2006, 34(4):1-17.
    [17]
    Henning J L. SPEC CPU2006 memory footprint. ACM SIGARCH Computer Architecture News, 2007, 35(1):84- 89.
    [18]
    Woo S C, Ohara M, Torrie E, Singh J P, Gupta A. The SPLASH-2 programs:Characterization and methodological considerations. ACM SIGARCH Computer Architecture News, 1995, 23(2):24-36.
    [19]
    Bienia C, Kumar S, Li K. PARSEC vs. SPLASH-2:A quantitative comparison of two multithreaded benchmark suites on chip-multiprocessors. In Proc. IEEE International Symposium on Workload Characterization, September 2008, pp.47-56.
    [20]
    Binkert N, Beckmann B, Black G et al. The gem5 simulator. ACM SIGARCH Computer Architecture News, 2011, 39(2):1-7.
    • Relative Articles

  • Related Articles

    [1]Xiao-Bing Chen, Hao Qi, Shao-Hui Peng, Yi-Min Zhuang, Tian Zhi, Yun-Ji Chen. Tetris: A Heuristic Static Memory Management Framework for Uniform Memory Multicore Neural Network Accelerators[J]. Journal of Computer Science and Technology, 2022, 37(6): 1255-1270. DOI: 10.1007/s11390-021-1213-3
    [2]Osamu Tatebe, Shukuko Moriwake, Yoshihiro Oyama. Gfarm/BB—Gfarm File System for Node-Local Burst Buffer[J]. Journal of Computer Science and Technology, 2020, 35(1): 61-71. DOI: 10.1007/s11390-020-9803-z
    [3]Ziqi Fan, Dongchul Park. Extending SSD Lifespan with Comprehensive Non-Volatile Memory-Based Write Buffers[J]. Journal of Computer Science and Technology, 2019, 34(1): 113-132. DOI: 10.1007/s11390-019-1902-3
    [4]Xue-Jun Yang, Jun-Jie Wu, Kun Zeng, Yu-Hua Tang. Managing Data-Objects in Dynamically Reconfigurable Caches[J]. Journal of Computer Science and Technology, 2010, 25(2): 232-245.
    [5]Xian-He Sun, Surendra Byna, Yong Chen. Server-Based Data Push Architecture for Multi-Processor Environments[J]. Journal of Computer Science and Technology, 2007, 22(5): 641-652.
    [6]Kyung-Oh Lee, Jun-Ho Park, Yoon-Young Park. Striping and Scheduling for Large Scale Multimedia Servers[J]. Journal of Computer Science and Technology, 2004, 19(6).
    [7]GU Ning, XU Xuebiao, SHI Baile. Design and Implementation of an Interoperable object Platform for Multi-Databases[J]. Journal of Computer Science and Technology, 2000, 15(3): 249-260.
    [8]LUO Junzhou, GU Guanqun, FEI Xiang. An Architectural Model for Intelligent Network Management[J]. Journal of Computer Science and Technology, 2000, 15(2): 136-143.
    [9]Gu Ning, Lin Zongkai, Guo Yuchai. On Model, Memory Management and Interface in EDBMS/3[J]. Journal of Computer Science and Technology, 1998, 13(4): 337-347.
    [10]Zhang Chenxi, Ci Yungui. Management of Statically Modifiable Prolog Code[J]. Journal of Computer Science and Technology, 1989, 4(4): 323-333.
    • Supplements (0)

Catalog

    Get Citation
    PDF
    XML
    Article views (50) PDF downloads (1105) Cited by()
    Related

    Copyright ©2025 JCST, All Rights Reserved     京ICP备05002829号-1

    Institute of Computing Technology, Chinese Academy of Sciences
    P.O. Box 2704, Beijing 100190, P.R. China

    Tel.: 86-10-62610746 E-mail: jcst@ict.ac.cn

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return