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Volume 38 Issue 1
January  2023
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Li JJ, Wang K, Zheng H et al. GShuttle: Optimizing memory access efficiency for graph convolutional neural network accelerators. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 38(1): 115−127 Jan. 2023. DOI: 10.1007/s11390-023-2875-9.
Citation: Li JJ, Wang K, Zheng H et al. GShuttle: Optimizing memory access efficiency for graph convolutional neural network accelerators. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 38(1): 115−127 Jan. 2023. DOI: 10.1007/s11390-023-2875-9.
shu

GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators

  • 1.

    School of Astronautics, Beihang University, Beijing 100191, China

  • 2.

    Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, Charlotte, NC 28223 U.S.A.

  • 3.

    Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816, U.S.A.

  • 4.

    Department of Electrical and Computer Engineering, George Washington University, Washington, DC 20052, U.S.A.

Funds: This work was supported by the U.S. National Science Foundation under Grant Nos. CCF-2131946, CCF-1953980, and CCF-1702980. Part of this work was conducted when Dr. Jia-Jun Li was a post-doctoral researcher at the HPCAT Laboratory, George Washington University.
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  • Author Bio:

    Jia-Jun Li received his B.E. degree from the Department of Automation, Tsinghua University, Beijing, in 2013. He received his Ph.D. degree from the Institute of Computing Technology, Chinese Academy of Sciences, Beijing, in 2019. From 2019 to 2021, he was a postdoc researcher with the Department of Electrical and Computer Engineering, George Washington University, Washington. He is currently an associate professor with the School of Astronautics, Beihang University, Beijing. His current research interests include machine learning and heterogeneous computer architecture

    Ke Wang received his Ph.D. degree in computer engineering from the George Washington University, Washington, in 2022. He received his M.S. degree in electrical engineering from Worcester Polytechnic Institute, Worcester, in 2015, and his B.S. degree in electrical engineering from Peking University, Beijing, in 2013. He is currently an assistant professor of the Department of Electrical and Computer Engineering at the University of North Carolina at Charlotte. His research work focuses on parallel computing, computer architecture, interconnection networks, and machine learning

    Hao Zheng received his Ph.D. degree in computer engineering from George Washington University, Washington, in 2021. He is an assistant professor in the Department of Electrical and Computer Engineering at the University of Central Florida, Orlando. His research interests are in the broad area of computer architecture and parallel computing, with emphasis on interconnection networks, AI chips for emerging applications, and energy-efficient manycore architecture designs

    Ahmed Louri is the David and Marilyn Karlgaard Endowed Chair Professor of the Department of Electrical and Computer Engineering at the George Washington University, Washington, which he joined in August 2015. He is also the director of the High Performance Computing Architectures and Technologies Laboratory. Dr. Louri received his Ph.D. degree in computer engineering from the University of Southern California, Los Angeles in 1988. From 1988 to 2015, he was a professor of Electrical and Computer Engineering at the University of Arizona, Tucson, and during that time, he served six years (2000 to 2006) as the chair of the Computer Engineering Program. From 2010 to 2013, Dr. Louri served as a program director in the National Science Foundation’s (NSF) Directorate for Computer and Information Science and Engineering. He directed the core computer architecture program and was on the management team of several cross-cutting programs. Dr. Louri conducts research in the broad area of computer architecture and parallel computing, with emphasis on interconnection networks, optical interconnects for scalable parallel computing systems, reconfigurable computing systems, and power-efficient and reliable Network-on-Chips (NoCs) for multicore architectures. Recently he has been concentrating on: energy-efficient, reliable, and high-performance many-core architectures; accelerator-rich reconfigurable heterogeneous architectures; machine learning techniques for efficient computing, memory, and interconnect systems; emerging interconnect technologies (photonic, wireless, RF, hybrid) for NoCs; future parallel computing models and architectures (including convolutional neural networks, deep neural networks, and approximate computing); and cloud-computing and data centers. He is the recipient of the 2020 IEEE Computer Society Edward J. McCluskey Technical Achievement Award, for pioneering contributions to the solution of on-chip and off-chip communication problems for parallel computing and manycore architectures. Dr. Louri is a fellow of IEEE, and he is currently the Editor-in-Chief of the IEEE Transactions on Computers. More information can be found at https://hpcat.seas.gwu.edu/Director.html

  • Received Date: September 28, 2022
  • Revised Date: October 27, 2022
  • Accepted Date: December 31, 2022
    Abstract

  • Graph convolutional neural networks (GCNs) have emerged as an effective approach to extending deep learning for graph data analytics, but they are computationally challenging given the irregular graphs and the large number of nodes in a graph. GCNs involve chain sparse-dense matrix multiplications with six loops, which results in a large design space for GCN accelerators. Prior work on GCN acceleration either employs limited loop optimization techniques, or determines the design variables based on random sampling, which can hardly exploit data reuse efficiently, thus degrading system efficiency. To overcome this limitation, this paper proposes GShuttle, a GCN acceleration scheme that maximizes memory access efficiency to achieve high performance and energy efficiency. GShuttle systematically explores loop optimization techniques for GCN acceleration, and quantitatively analyzes the design objectives (e.g., required DRAM accesses and SRAM accesses) by analytical calculation based on multiple design variables. GShuttle further employs two approaches, pruned search space sweeping and greedy search, to find the optimal design variables under certain design constraints. We demonstrated the efficacy of GShuttle by evaluation on five widely used graph datasets. The experimental simulations show that GShuttle reduces the number of DRAM accesses by a factor of 1.5 and saves energy by a factor of 1.7 compared with the state-of-the-art approaches.

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