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Volume 30 Issue 1
January  2015
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Qi Wang, Jia-Rui Li, Dong-Hui Wang. Improving the Performance and Energy Efficiency of Phase Change Memory Systems[J]. Journal of Computer Science and Technology, 2015, 30(1): 110-120. DOI: 10.1007/s11390-015-1508-3
Citation: Qi Wang, Jia-Rui Li, Dong-Hui Wang. Improving the Performance and Energy Efficiency of Phase Change Memory Systems[J]. Journal of Computer Science and Technology, 2015, 30(1): 110-120. DOI: 10.1007/s11390-015-1508-3
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Improving the Performance and Energy Efficiency of Phase Change Memory Systems

  • 1 Digital System Integration Laboratory, Institute of Acoustics, Chinese Academy of Sciences, Beijing 100190, China;
    2 University of Chinese Academy of Sciences, Beijing 100049, China

Funds: This work was supported by the National Science and Technology Major Projects of China under Grant No. 2009ZX01 034-001-002-005 and the Knowledge Innovation Project of Institute of Acoustics, Chinese Academy of Sciences.
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  • Author Bio:

    Qi Wang received her B.S. degree in electronic information science and technology from Lanzhou University in 2011. She is now a Ph.D. candidate in Institute of Acoustics, Chinese Academy of Sciences, Beijing. Her research interests include VLSI design, computer architecture, and emerging memory technologies.

  • Received Date: July 12, 2014
  • Revised Date: December 17, 2014
  • Published Date: January 04, 2015
    Abstract
  • Phase change memory (PCM) is a promising technology for future memory thanks to its better scalability and lower leakage power than DRAM (dynamic random-access memory). However, adopting PCM as main memory needs to overcome its write issues, such as long write latency and high write power. In this paper, we propose two techniques to improve the performance and energy-efficiency of PCM memory systems. First, we propose a victim cache technique utilizing the existing buffer in the memory controller to reduce PCM memory accesses. The key idea is reorganizing the buffer into a victim cache structure (RBC) to provide additional hits for the LLC (last level cache). Second, we propose a chip parallelism-aware replacement policy (CPAR) for the victim cache to further improve performance. Instead of evicting one cache line once, CPAR evicts multiple cache lines that access different PCM chips. CPAR can reduce the frequent victim cache eviction and improve the write parallelism of PCM chips. The evaluation results show that, compared with the baseline, RBC can improve PCM memory system performance by up to 9.4% and 5.4% on average. Combing CPAR with RBC (RBC+CPAR) can improve performance by up to 19.0% and 12.1% on average. Moreover, RBC and RBC+CPAR can reduce memory energy consumption by 8.3% and 6.6% on average, respectively.
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