Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization

In view of the significant number of defective nanodevices in the Cmos/nanowire/MOLecular hybrid (CMOL) circuit, defect-tolerant mapping is an essential step to achieve correct logic operations in defective CMOL circuits. However, less effort has been made to improve circuit delay by defect-tolerant strategies. In this paper, the factors affecting the delay of mapped circuits are analyzed, and the path-tree based defect-tolerant mapping method for the delay optimization is proposed. From the logic-domain, the terminology of the path tree is presented, and the logic circuit is first partitioned into multiple path trees. Then, the mapping areas in the physic-domain are pre-planned for (near) critical path trees. During the mapping process, the specific mapping modes and an updating strategy are formulated to map the path trees:inputs are mapped based on input sorting; (near) critical path trees are mapped with priority, while the others are mapped in a hierarchical way. Finally, an improved tabu search algorithm is employed to verify the validity of the proposed defect-tolerant mapping method. Experimental evaluations on the ISCAS benchmarks show that the proposed method can reduce circuit delay by 15.22%.