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Volume 38 Issue 2
March  2023
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Li T, Jiang HL, Mo H et al. Approximate processing element design and analysis for the implementation of CNN accelerators. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 38(2): 309−327 Mar. 2023. DOI: 10.1007/s11390-023-2548-8.
Citation: Li T, Jiang HL, Mo H et al. Approximate processing element design and analysis for the implementation of CNN accelerators. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 38(2): 309−327 Mar. 2023. DOI: 10.1007/s11390-023-2548-8.
shu

Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators

  • 1.

    Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai 200240, China

  • 2.

    School of Integrated Circuits, Tsinghua University, Beijing 100084, China

  • 3.

    Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB T6G 1H9, Canada

Funds: This work was supported in part by the National Natural Science Foundation of China under Grant No. 62104127 and the National Key Research and Development Program of China under Grant No. 2022YFB4500200.
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  • Author Bio:

    Tong Li received his Bachelor's degree in electronic information engineering from College of Electronic Science and Engineering, Jilin University, Changchun, in 2016. He is currently pursuing his Ph.D. degree with the Department of Micro-Nano Electronics at Shanghai Jiao Tong University, Shanghai. His research interests include high energy efficient arithmetic circuit design and SoC design

    Hong-Lan Jiang received her B.Sc. and Master's degrees in instrument science and technology from Harbin Institute of Technology, Harbin, in 2011 and 2013, respectively. In 2018, she received her Ph.D. degree in integrated circuits and systems from University of Alberta, Edmonton. From 2018 to 2021, she worked as a postdoctoral fellow with the School of Integrated Circuits, Tsinghua University, Beijing. She is currently an associate professor with the Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai. Her research interests include approximate computing, reconfigurable computing, and stochastic computing. She serves as an associate editor for Microelectronics Reliability. She is a member of CCF and IEEE

    Hai Mo received his B.S. degree in computer science from Huazhong University of Science and Technology, Wuhan, in 2019. He received his M.S. degree in integrated circuit engineering from the School of Integrated Circuits at Tsinghua University, Beijing, in 2022. His research interest spans the area of architecture design, in-memory computing, and hardware implementation for deep learning accelerators

    Jie Han received his B.Sc. degree in electronic engineering from Tsinghua University, Beijing, in 1999, and his Ph.D. degree in applied physics from the Delft University of Technology, Delft, in 2004. He is currently a professor and program director of computer engineering in the Department of Electrical and Computer Engineering, University of Alberta, Edmonton. His research interests include approximate computing, stochastic computing, reliability and fault tolerance, nanoelectronic circuits and systems, novel computational models for nanoscale and biological applications. He was a recipient of the Best Paper Award at NANOARCH 2015 and DATE 2023, and Best Paper Nominations at GLSVLSI 2015, NANOARCH 2016, ISQED 2018 and DATE 2022. He was nominated for the 2006 Christiaan Huygens Prize of Science by the Royal Dutch Academy of Science. His work was recognized by Science, for developing a theory of fault-tolerant nanocircuits in 2005. He served as a general chair for NANOARCH 2021, GLSVLSI 2017 and DFT 2013, and a technical program committee chair for NANOARCH 2022, GLSVLSI 2016, DFT 2012, and the Symposium on Stochastic and Approximate Computing for Signal Processing and Machine Learning in 2017. He serves (or has served) as an associate editor for the IEEE Transactions on Emerging Topics in Computing (TETC), the IEEE Transactions on Nanotechnology, the IEEE Circuits and Systems Magazine, the IEEE Open Journal of the Computer Society, Microelectronics Reliability and the Journal of Electronic Testing: Test and Application (JETTA, Elsevier). He is a senior member of IEEE

    Lei-Bo Liu received his B.S. degree in electronic engineering and his Ph.D. degree in electronic engineering with the Institute of Microelectronics, both from Tsinghua University, Beijing, in 1999 and 2004, respectively. He is currently a full professor with the School of Integrated Circuits, Tsinghua University, Beijing. His current research interests include reconfigurable computing, mobile computing, and very large-scale integration digital signal processing

    Zhi-Gang Mao received his Ph.D. degree in electronic engineering from Rennes University, Rennes, in 1992. He is currently a professor with the Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai. His current research interests include VLSI (very large scale integration) design methodology, high-speed digital circuit design technology, signal processor architecture, and hardware security technology and reliability in semiconductor devices

  • Corresponding author:

    honglan@sjtu.edu.cn

  • Received Date: June 02, 2022
  • Accepted Date: March 22, 2023
    Abstract

  • As a primary computation unit, a processing element (PE) is key to the energy efficiency of a convolutional neural network (CNN) accelerator. Taking advantage of the inherent error tolerance of CNNs, approximate computing with high hardware efficiency has been considered for implementing the computation units of CNN accelerators. However, individual approximate designs such as multipliers and adders can only achieve limited accuracy and hardware improvements. In this paper, an approximate PE is dedicatedly devised for CNN accelerators by synergistically considering the data representation, multiplication and accumulation. An approximate data format is defined for the weights using stochastic rounding. This data format enables a simple implementation of multiplication by using small lookup tables, an adder and a shifter. Two approximate accumulators are further proposed for the product accumulation in the PE. Compared with the exact 8-bit fixed-point design, the proposed PE saves more than 29% and 20% in power-delay product for 3 × 3 and 5 × 5 sum of products, respectively. Also, compared with the PEs consisting of state-of-the-art approximate multipliers, the proposed design shows significantly smaller error bias with lower hardware overhead. Moreover, the application of the approximate PEs in CNN accelerators is analyzed by implementing a multi-task CNN for face detection and alignment. We conclude that 1) an approximate PE is more effective for face detection than for alignment, 2) an approximate PE with high statistically-measured accuracy does not necessarily result in good quality in face detection, and 3) properly increasing the number of PEs in a CNN accelerator can improve its power and energy efficiency.

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