Survey of Coarse-Grained Reconfigurable Architectures Mapping Algorithms

This paper presents a comprehensive survey of mapping algorithms for coarse-grained reconfigurable architecture (CGRA), which have emerged as promising and popular accelerators in wireless communication chips in the era of Industry 4.0. To address the limitations of traditional application-specific integrated circuit (ASIC), which incur high single tape-out costs and suffer from inflexibility, as well as the design redundancies and high power consumption of digital signal processor (DSP) in wireless processing scenarios, CGRA achieve high flexibility and low energy consumption through reconfigurable processing element (PE) with interconnections. Mapping applications onto CGRA is a crucial step in achieving efficient acceleration functionality, and numerous mapping algorithms have been proposed to address this challenge. This paper clarifies that the essence of CGRA mapping lies in the mapping between tasks and PEs, analyzes core features of task description graphs and hardware architecture description graphs. It decomposes the three-stage process and bottlenecks of mapping to help researchers grasp key concepts. It also analyzes mainstream mapping algorithms, deduces their suitable task and hardware features, forms a table for scenario-based selection, organises machine learning's mapping application paradigms to offer innovation paths, and analyzes general algorithms for communication scenarios to support researchers' selection.