We use cookies to improve your experience with our site.

Indexed in:

SCIE, EI, Scopus, INSPEC, DBLP, CSCD, etc.

Submission System
(Author / Reviewer / Editor)
Hai-Long Yao, Yi-Ci Cai, Qiang Zhou, Xian-Long Hong. Crosstalk-Aware Routing Resource Assignment[J]. Journal of Computer Science and Technology, 2005, 20(2).
Citation: Hai-Long Yao, Yi-Ci Cai, Qiang Zhou, Xian-Long Hong. Crosstalk-Aware Routing Resource Assignment[J]. Journal of Computer Science and Technology, 2005, 20(2).

Crosstalk-Aware Routing Resource Assignment

More Information
  • Published Date: March 14, 2005
  • Crosstalk noise is one of the emerging issues in deep sub-micrometer technology which causes many undesired effects on the circuit performance. In this paper, a Crosstalk-Aware Routing Resource Assignment (CARRA) algorithm is proposed, which integrates the routing layers and tracks to address the crosstalk noise issue during the track/layer assignment stage. The CARRA problem is formulated as a weighted bipartite matching problem and solved using the linear assignment algorithm. The crosstalk risks between nets are represented by an undirected graph and the maximum number of the concurrent crosstalk risking nets is computed as the max clique of the graph. Then the nets in each max clique are assigned to disadjacent tracks. Thus the crosstalk noise can be avoided based on the clique concept. The algorithm is tested on IBM benchmarks and the experimental results show that it can improve the final routing layout a lot with little loss of the completion rate.
  • Related Articles

    [1]Kai Liu, Ke-Yan Wang, Yun-Song Li, Cheng-Ke Wu. A Novel VLSI Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme[J]. Journal of Computer Science and Technology, 2007, 22(5): 661-672.
    [2]Yi-Ci Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xian-Long Hong. Priority-Based Routing Resource Assignment Considering Crosstalk[J]. Journal of Computer Science and Technology, 2006, 21(6): 913-921.
    [3]Li Zhang, Don Xie, Di Wu. Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard[J]. Journal of Computer Science and Technology, 2006, 21(3): 378-382.
    [4]J. M. Gallière, M. Renovell, F. Azais, Y. Bertrand. Delay Testing Viability of Gate Oxide Short Defects[J]. Journal of Computer Science and Technology, 2005, 20(2): 201-209.
    [5]Dian Zhou, Rui-Ming Li. Design and Verification of High-Speed VLSI Physical Design[J]. Journal of Computer Science and Technology, 2005, 20(2): 147-165.
    [6]Song Chen, Xian-Long Hong, She-Qin Dong, Yu-Chun Ma, Chung-Kuan Cheng, Jun Gu. Fast Evaluation of Bounded Slice-Line Grid[J]. Journal of Computer Science and Technology, 2004, 19(6).
    [7]LIU Thnpei. Orthogonal Drawings of Graphs for the Automation of VLSI Circuit Design[J]. Journal of Computer Science and Technology, 1999, 14(5): 447-459.
    [8]Chung-Han CHEN. Embedding Binary Tree in VLSI/WSI Processor Array[J]. Journal of Computer Science and Technology, 1996, 11(3): 326-336.
    [9]Chen Qingfang, Wei Daozheng. DLJ:A Dynamic Line-Justification Algorithm for Test Generation[J]. Journal of Computer Science and Technology, 1993, 8(1): 87-91.
    [10]Feng Yulin. Recursive Implementation of VLSI Circuits[J]. Journal of Computer Science and Technology, 1986, 1(2): 72-82.

Catalog

    Article views (24) PDF downloads (1455) Cited by()
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return