The Value of a Small Microkernel for Dreamy Memory and the RAMpageMemory Hierarchy

This paper explores potential for the RAMpage memory hierarchy to use amicrokernel with a small memory footprint, in a specialized cache-speedstatic RAM (tightly-coupled memory, TCM). Dreamy memory is DRAMkept in low-power mode, unless referenced. Simulations show that asmall microkernel suits RAMpage well, in that it achieves significantlybetter speed and energy gains than a standard hierarchy from adding TCM.RAMpage, in its best 128KB L2 case, gained 11% speed using TCM, andreduced energy 14%. Equivalent conventional hierarchy gains were under1%. While 1MB L2 was significantly faster against lower-energy casesfor the smaller L2, the larger SRAM's energy does not justify the speedgain. Using a 128KB L2 cache in a conventional architecture resulted ina best-case overall run time of 2.58s, compared with the best dreamymode run time (RAMpage without context switches on misses) of 3.34s, aspeed penalty of 29%. Energy in the fastest 128KB L2 case was 2.18Jvs. 1.50J, a reduction of 31%. The same RAMpage configurationwithout dreamy mode took 2.83s as simulated, and used 2.39J, anacceptable trade-off (penalty under 10%) for being able to switcheasily to a lower-energy mode.