Micro-Task Processing in Heterogeneous Reconfigurable Systems

New reconfigurable computing architectures are introduced to overcomesome of the limitations of conventional microprocessors and fine-grainedreconfigurable devices (e.g., FPGAs). One of the new promisingarchitectures are Configurable System-on-Chip (CSoC) solutions. Theywere designed to offer high computational performance for real-timesignal processing and for a wide range of applications exhibiting highdegrees of parallelism. The programming of such systems is an inherentlychallenging problem due to the lack of an programming model.This paper describes a novel heterogeneous system architecture forsignal processing and data streaming applications. It offers highcomputational performance and a high degree of flexibility andadaptability by employing a micro Task Controller (mTC) unit inconjunction with programmable and configurable hardware. Thehierarchically organized architecture provides a programming model,allows an efficient mapping of applications and is shown to be easyscalable to future VLSI technologies. Several mappings of commonly useddigital signal processing algorithms for future telecommunication andmultimedia systems and implementation results are given for astandard-cell ASIC design realization in 0.18 micron 6-layer UMCCMOS technology.