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Citation: | Yi-Ci Cai, Xin Zhao, Qiang Zhou, Xian-Long Hong. Shielding Area Optimization Under the Solution of Interconnect Crosstalk[J]. Journal of Computer Science and Technology, 2005, 20(6): 901-906. |
[1] |
He L, Lepak K M. Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization. In Proc. International Symposiums on Physical Design , San Diego, CA, April 9--12, 2000, pp.55--60.
|
[2] |
Gao T, Liu C L. Minimum crosstalk channel routing. In Proc. the IEEE Int. Conf. Computer-Aided Design , Santa Clara, CA, Nov. 7--11, 1993, pp.692--696.
|
[3] |
Gao T, Liu C L. Minimum crosstalk switchbox routing. In Proc. the IEEE Int. Conf. Comupter-Aided Design , San Jose, CA, Nov. 6--10, 1994, pp.610--615.
|
[4] |
Yim J S, Kyung C M. Reducing cross-coupling among interconnect wires in deep-submicron datapath design. In Proc. ACM/IEEE Design Automation Conference , New Orleans, LA, June 21--25, 1999, pp.485--489.
|
[5] |
Xue T, Kuh E S. Post global routing crosstalk synthesis. IEEE Trans. CAD , Dec. 1997, 16(12): 1418--1430.
|
[6] |
Chang C C, Cong J. Pseudo pin assignment with crosstalk noise control. In Proc. International Symposiums on Physical Design , San Diego, CA, April 9--12, 2000, pp.41--47.
|
[7] |
Jinan Lou, Wei Chen. Cross talk driven placement. In Proc. the Asia and South Pacific Design Automation Conference'03 , Japan, Jan. 21--23, 2003, pp.735--740.
|
[8] |
Lepak K M, Luwandi I, He L. Shield insertion and net ordering under explicit RLC noise constraint. In Proc. ACM/IEEE Design Automation Conference , Las Vegas, NV, June 18--22, 2001, pp.199--202.
|
[9] |
He L. Interconnect Modeling and Design with Consideration of On-Chip Inductance. Chapter 5 in -Layout Optimization in VLSI Designs , Du D Z, Sapatnekar S (eds.), Norwell, MA: Kluwer, 2001, pp.155--190.
|
[10] |
Yehia M, Steve M, Jamil K et al. Managing on-chip inductive effects. IEEE Trans. VLSI , Dec. 2002, 10(6): 789--798.
|
[11] |
Cai Yici, Zhao Xin, Hong Xianlong. Progress and research on interconnects crosstalk in deep submicron technology. Chinese Journal of Semiconductors , 2003, 24(11): 1121--1129.
|
[12] |
Lepak K M, Xu M, Chen J, He L. Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization. ACM Trans. Design Automation of Electronic System , 2004, 9(3): 290--309.
|
[13] |
Chen J, He L. Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects. In Proc. the Asia and South Pacific Design Automation Conference'03 , Japan, Jan. 21--24, 2003, pp.162--167.
|
[14] |
Venkatesan R, Davis J A, Meindl J D. Compact distributed RLC interconnect models---Part IV: Unified models for time delay, crosstalk, and repeater insertion. IEEE Trans. Electron Devices , April 2003, 50(4): 1094--1102.
|
[15] |
He L, Xu M. Modeling and layout optimization for on-chip inductive coupling. U. Wisconsin at Madison, Technical Report ECE-00-1.
|
[16] |
Lin S, Chang N, Nakagawa O S. Quick on-chip selfand mutual-inductance screen. In Proc. Int. Symposium on Quality of Electronic Design , San Jose, CA, March 20--22, 2000, pp.513--520.
|
[17] |
Xiong Junjun, He Lei. Full-chip routing optimization with RLC crosstalk budgeting. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems , March 2004, 23(3): 366--377.
|
[18] |
Ruehli A. Equivalent circuit models for three-dimensional multiconductor systems. IEEE Trans. MIT , 1974, pp.216--221.
|
[19] |
He L, Chang N, Lin S, Nakagawa O S. An efficient inductance modeling for on-chip interconnects. In Proc. the IEEE 1999 Custom Integrated Circuits Conference , San Diego, CA, May 16--19, 1999, pp.457--460.
|
[20] |
Ma J D, He L. Formulae and applications of interconnect estimation considering shielding insertion and net ordering. In Proc. the IEEE Int. Conf. Computer-Aided Design , San Jose, CA, Nov. 4--8, 2001, pp.327--332.
|