An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder

In the part 2 of advanced Audio Video coding Standard(AVS-P2), many efficient coding tools are adopted in motioncompensation, such as new motion vector prediction, symmetric matching,quarter precision interpolation, etc. However, these new featuresenormously increase the computational complexity and the memorybandwidth requirement, which make motion compensation a difficultcomponent in the implementation of the AVS HDTV decoder. This paperproposes an efficient motion compensation architecture for AVS-P2 videostandard up to the Level 6.2 of the Jizhun Profile. It has amacroblock-level pipelined structure which consists of MV predictorunit, reference fetch unit and pixel interpolation unit. The proposedarchitecture exploits the parallelism in the AVS motion compensationalgorithm to accelerate the speed of operations and uses the dedicateddesign to optimize the memory access. And it has been integrated in aprototype chip which is fabricated with TSMC 0.18-um CMOS technology,and the experimental results show that this architecture can achieve the real timeAVS-P2 decoding for the HDTV 1080i (1920 * 1088 4:2:0 60field/s) video.The efficient design can work at the frequency of 148.5MHz and thetotal gate count is about 225K.