Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

This paper introduces the microarchitecture and physical implementationof the Godson-2E processor, which is a four-issue superscalar RISCprocessor that supports the 64-bit MIPS instruction set. The adoption ofthe aggressive out-of-order execution and memory hierarchy techniqueshelp Godson-2E to achieve high performance. The Godson-2E processor hasbeen physically designed in a 7-metal 90nm CMOS process using thecell-based methodology with some bit-sliced manual placement and anumber of crafted cells and macros. The processor can be run at 1GHz andachieves a SPEC CPU2000 rate higher than 500.