An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking

Mainstream processors implement the instructionscheduler using a monolithic CAM-based issue queue (IQ), which consumesincreasingly high energy as its size scales. In particular, itsinstruction wakeup logic accounts for a major portion of the consumedenergy. Our study shows that instructions with 2 non-ready operands(called 2OP instructions) are in small percentage, but tend to spendlong latencies in the IQ. They can be effectively shelved in a smallRAM-based waiting instruction buffer (WIB) and steered into the IQ atappropriate time. With this two-level shelving ability, half of the CAMtag comparators are eliminated in the IQ, which significantly reducesthe energy of wakeup operation. In addition, we propose an adaptivebanking scheme to downsize the IQ and reduce the bit-width of tagcomparators. Experiments indicate that for an 8-wide issue superscalaror SMT processor, the energy consumption of the instruction schedulercan be reduced by 67%. Furthermore, the new design has potentiallyfaster scheduler clock speed while maintaining close IPC to themonolithic scheduler design. Compared with the previous work on eliminatingtags through prediction, our design is superior in terms of both energyreduction and SMT support.