A Yield-Driven Gridless Router

A new gridless router to improve the yield of IC layoutis presented. The improvement of yield is achieved by reducing thecritical areas where the circuit failures are likely to happen. Thisgridless area router benefits from a novel cost function to computecritical areas during routing process, and heuristically lays thepatterns on the chip area where it is less possible to induce criticalarea. The router also takes other objectives into consideration, suchas routing completion rate and nets length. It takes advantage ofgridless routing to gain more flexibility and a higher completion rate.The experimental results show that critical areas are effectivelydecreased by 21% on average while maintaining the routing completionrate over 99%.