Low Cost Scan Test by Test Correlation Utilization

Scan-based testing methodologies remedy the testability problem ofsequential circuits; yet they suffer from prolonged test time andexcessive test power due to numerous shift operations. Thecorrelation among test data along with the high density of theunspecified bits in test data enables the utilization of theexisting test data in the scan chain for the generation of thesubsequent test stimulus, thus reducing both test time and testdata volume. We propose a pair of scan approaches in this paper;in the first approach, a test stimulus partially consists of thepreceding stimulus, while in the second approach, a test stimuluspartially consists of the preceding test response bits. Bothproposed scan-based test schemes access only a subset of scancells for loading the subsequent test stimulus while freezing theremaining scan cells with the preceding test data, thus decreasingscan chain transitions during shift operations. The proposed scanarchitecture is coupled with test data manipulation techniqueswhich include test stimuli ordering and partitioning algorithms,boosting test time reductions. The experimental results confirmthat test time reductions exceeding 97\%, and test powerreductions exceeding 99\% can be achieved by the proposedscan-based testing methodologies on larger ISCAS89 benchmarkcircuits.