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Tang Zhimin, Xia Peisu. A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array[J]. Journal of Computer Science and Technology, 1995, 10(2): 97-103.
Citation:
Tang Zhimin, Xia Peisu. A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array[J]. Journal of Computer Science and Technology, 1995, 10(2): 97-103.
Tang Zhimin, Xia Peisu. A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array[J]. Journal of Computer Science and Technology, 1995, 10(2): 97-103.
Citation:
Tang Zhimin, Xia Peisu. A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array[J]. Journal of Computer Science and Technology, 1995, 10(2): 97-103.
A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array
This paper describes a maximum time difference pipelined arithmetic chip,the 36-bit adder and subtractor based on 1.5 μm CMOS gate array The chipcan operate at 60MHz, and consumes less than 0.5Wat. The results are alsostudied, and a more precise model of delay time dmerence is proposed.
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