Embedding Binary Tree in VLSI/WSI Processor Array

Many reconfiguration schemes for fault-tolerant binary tree architectures have been proposed in the lite..t.re1-6. The VLSI layouts of most previous studies are based on the classical H-tree layout, resulting in low area utilization and likely an unnecessarily high manufacturing cost simply due to the waste of a significaot portion of silicon area. In this paper, we present an area-efficient approach to the reconfigurable binary tree architecture. Area utilization and interconnection complexity of our des…