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Volume 11 Issue 3
May  1996
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Chung-Han CHEN. Embedding Binary Tree in VLSI/WSI Processor Array[J]. Journal of Computer Science and Technology, 1996, 11(3): 326-336.
Citation: Chung-Han CHEN. Embedding Binary Tree in VLSI/WSI Processor Array[J]. Journal of Computer Science and Technology, 1996, 11(3): 326-336.
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Embedding Binary Tree in VLSI/WSI Processor Array

  • Computer Science Department; Tuskegee University Tuskegee; Alabama 36088; US.A.;

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  • Published Date: May 09, 1996
    Abstract
  • Many reconfiguration schemes for fault-tolerant binary tree architectures have been proposed in the lite..t.re[1-6]. The VLSI layouts of most previous studies are based on the classical H-tree layout, resulting in low area utilization and likely an unnecessarily high manufacturing cost simply due to the waste of a significaot portion of silicon area. In this paper, we present an area-efficient approach to the reconfigurable binary tree architecture. Area utilization and interconnection complexity of our des…
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    • References (3)
  • [1]
    Belkhale.K.P, Banerjee.P. Reconfiguration strategies for VLSI arrays and trees using a modified diogense approach. IEEE Trans.on Computers, 1992, C-41(1): 83-96.
    [2]
    Singh.A, Youn.H.Y. Modular fault-tolerant binary tree architecture with short links. IEEE Trans.on Computers, 1991, C-40(7): 882-890.
    [3]
    Chen Y Y, Upadhyaya S. Reliability, re-configuration, and spare allocation issues in binary architecture based on multiple-level redundancy. IEEE Trans.on Computers, 1993, C-42(6): 713-723. ……….
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