An Analytical Delay Model

Delay considerttion has been a major issue in design and test of high performance digital circuits . The assumption of input signal change occurring only when all internal nodes are stable restricts the increase of clock frequency. It is no longer true for wave pipelining circuits. However, previous logical delay models are based on the assumption. In addition, the stable time of a robust delay test generally depends on the longest sensitizable path delay. Thus , a new delay model is desirable. This paper e…