A Loop-Based Apparatus for At-Speed Self-Testing

At-speed testing using external tester requires an expensiveequipment, thus built-in self-test (BIST) is an alternative technique due toits ability to perform on-chip at-speed self-testing. The main issue inBIST for at-speed testing is to obtain high delay fault coverage with alow hardware overhead. This paper presents an improved loop-based BISTscheme, in which a configurable MISR (multiple-input signature register) isused to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transition-graph ofthe proposed BIST scheme are analyzed. Based on it, an approach todesign and efficiently implement the proposed BIST scheme is developed.Experimental results on academic benchmark circuits are presented todemonstrate the effectiveness of the proposed BIST scheme as well asthe design approach.