BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count

This paper presents a built-in self-test (BIST) scheme for detecting allrobustly testable multiple stuck-open faults confined to any singlecomplex cell of a CMOS circuit. The test pattern generator (TPG)generates all n.2^n single-input-change (SIC) ordered testpairs for an n-input circuit-under-test (CUT) contained in a sequence oflength 2n\.2^n. The proposed design is universal, i.e.,independent of the structure and functionality of the CUT. A counterthat counts the number of alternate transitions at the output of theCUT, is used as a signature analyzer (SA). The design of TPG and SA issimple and no special design- or synthesis-for-testability techniquesand/or additional control lines are needed.