Evaluation and Choice of Various Branch Predictors for Low-Power Embedded Processor

Power is an important design constraint in embeddedcomputing systems. To meet the power constraint, microarchitecture andhardware designed to achieve high performance need to be revisited,from both performance and power angles. This paper studies one ofthem: branch predictor. As well known, branch prediction is critical toexploit instruction level parallelism effectively, but may incuradditional power consumption due to the hardware resource dedicated forbranch prediction and the extra power consumed on mispredictedbranches. This paper explores the design space of branch predictionmechanisms and tries to find the most beneficial one to realizelow-power embedded processor. The sample processor studied isGodson-like processor, which is a dual-issue, out-of-order processorwith deep pipeline, supporting MIPS instruction set.