Abstract: As an emerging computing technology, approximate computing enables computing systems to utilize hardware resources efficiently. Recently, approximate arithmetic units have received extensive attention and have been employed as hardware modules to build approximate circuit systems, such as approximate accelerators. In order to make the approximate circuit system meet the application requirements, it is imperative to quickly estimate the error quality caused by the approximate unit, especially in the high-level synthesis of the approximate circuit. However, there are few studies in the literature on how to efficiently evaluate the errors in the approximate circuit system. Hence, this paper focuses on error evaluation techniques for circuit systems consisting of approximate adders and approximate multipliers, which are the key hardware components in fault-tolerant applications. In this paper, the characteristics of probability mass function (PMF) based estimation are analyzed initially, and then an optimization technique for PMF-based estimation is proposed with consideration of these features. Finally, experiments prove that the optimization technology can reduce the time required for PMF-based estimation and improve the estimation quality.