Abstract: The on-chip memory performance of embedded systems directly affects thesystem designers' decision about how to allocate expensive silicon area.A novel memory architecture, flexible sequentialand random access memory (FSRAM), is investigated for embedded systems.To realize sequential accesses, small ``links'' are added to each row in the RAMarray to point to the next row to be prefetched. The potential cachepollution is ameliorated by a small sequential access buffer(SAB). To evaluate the architecture-level performance of FSRAM, we ranthe Mediabench benchmark programs on a modified version of theSimpleScalar simulator. Our results show that the FSRAM improvesthe performance of a baseline processor with a 16KB data cache up to55%, with an average of 9%; furthermore, the FSRAM reduces 53.1% ofthe data cache miss count on average due to its prefetching effect. Wealso designed RTL and SPICE models of the FSRAM, which show thatthe FSRAM significantly improves memory access time, while reducingpower consumption, with negligible area overhead.