Abstract: In this paper, we propose a VLSI architecture thatperforms the line-based discrete wavelet transform (DWT) using alifting scheme. The architecture consists of row processors, columnprocessors, an intermediate buffer and a control module. Row processorand Column processor work as the horizontal and vertical filtersrespectively. Intermediate buffer is composed of five FIFOs to storetemporary results of horizontal filter. Control module schedules theoutput order to external memory. Compared with existing ones, thepresented architecture parallelizes all levels of wavelet transform tocompute multilevel DWT within one image transmission time, and uses noexternal but one intermediate buffer to store several line results ofhorizontal filtering, which decreases resource required significantlyand reduces memory efficiently. This architecture is suitable forvarious real-time image/video applications.