摘要: This paper studies the realization of the high level synthesis fromsystem behavioral (algorithmic or functional) description of circuits to structuraldescription of RTL and logic level. Based on Xilinx-FPGA libraryl the structural description is mapped to technology-dependent ASIC, and FPGA chips are generated.The main points in this paper include the technical decision of each subsystem in aVHDL high level synthesis system HLS/BIT. The system is realized on SUN SPARC2, and correct running results are given…