DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged SSDs
TLC (Triple-Level Cell) NAND flash is increasingly adopted to build SSDs (Solid-State Drives) for modern computer systems. While TLC NAND flash effectively improves storage density, it faces severe reliability issues, in particular, the pages stored using different bits exhibit different BERs (bit error rates). Integrating strong LDPC (Low-Density Parity-Check code) helps to improve reliability but suffers from long and proportional read latency due to multiple read retries.
In this paper, we propose DIR, a novel strategy for improving the performance of TLC NAND flash-based SSDs, in particular, the aged ones with large BERs. DIR exploits the observation that the latency of an I/O request is determined, without considering the queuing time, by the access of the slowest device page, i.e., the page that has the highest BER. By grouping consecutive logical pages that have high locality, and interleaving their encoded data in different types of device pages that have different BERs, DIR effectively reduces the number of read retries for LDPC. To reduce the read amplification issue because of one logic page residing on more than one physical pages, we also design a page-interleaving friendly page allocation scheme, which utilize the enhanced multi-plane command to issue multi parallel reads for one logic page, leading to reduced read latency and increasing plane-level parallelism.
Our experimental results show that adopting DIR in aged SSDs exploits nearly 33% locality from I/O requests, and, on average, reduces 43% read latency over conventional aged SSDs.