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Volume 38 Issue 4
July  2023
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Xu YN, Yu ZH, Wang KF et al. Functional verification for agile processor development: A case for workflow integration. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 38(4): 737−753 July 2023. DOI: 10.1007/s11390-023-3285-8.
Citation: Xu YN, Yu ZH, Wang KF et al. Functional verification for agile processor development: A case for workflow integration. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 38(4): 737−753 July 2023. DOI: 10.1007/s11390-023-3285-8.
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Functional Verification for Agile Processor Development: A Case for Workflow Integration

  • 1.

    State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China

  • 2.

    University of Chinese Academy of Sciences, Beijing 100049, China

  • 3.

    Beijing Institute of Open Source Chip, Beijing 100080, China

Funds: This work was supported in part by the Strategic Priority Research Program of Chinese Academy of Sciences (CAS) under Grant No. XDC05030200, the National Key Research and Development Program of China under Grant No. 2022YFB4500403, the National Natural Science Foundation of China under Grant Nos. 62090022 and 62172388, the Youth Innovation Promotion Association of the Chinese Academy of Sciences under Grant No. 2020105, and the Innovation Grant No. E261100 by Institute of Computing Technology, Chinese Academy of Sciences.
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  • Author Bio:

    Yi-Nan Xu received his B.Eng. degree in computer science and technology from the University of Chinese Academy of Sciences, Beijing, in 2019. He is currently a Ph.D. candidate at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing. His research interests include agile development of processors and processor microarchitecture

    Zi-Hao Yu received his Ph.D. degree in computer systems organization from the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), Beijing, in 2022. He is currently an engineer at ICT, CAS. His research interests include computer architecture and operating systems

    Kai-Fan Wang received his B.Eng. degree in computer science and technology from the University of Chinese Academy of Sciences, Beijing, in 2020. He is currently a Ph.D. candidate at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing. His research interests include agile development of processors and processor microarchitecture

    Hua-Qiang Wang received his B.Eng. degree in computer science and technology from the University of Chinese Academy of Sciences, Beijing, in 2020. He is currently a Master student at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing. His research interests include processor microarchitecture and open-source hardware design

    Jia-Wei Lin received his B.Eng. degree in computer science and technology from the University of Chinese Academy of Sciences, Beijing, in 2020. He is currently a Master student at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing. His research interests include high-performance computer architecture

    Yue Jin received his B.Eng. degree in computer science and technology from the University of Chinese Academy of Sciences, Beijing, in 2020. He is currently a Ph.D. candidate at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing. His research interests include high performance processor design, computer architecture security, and processor verification

    Lin-Juan Zhang received her B.Eng. degree in computer science and technology from the University of Chinese Academy of Sciences, Beijing, in 2020. She is currently a Master student at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing. Her research interests include high-performance computer architecture

    Zi-Fei Zhang received his B.Eng. degree in computer science and technology from the University of Chinese Academy of Sciences, Beijing, in 2020. He is currently a Ph.D. candidate at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing. His research interests include computer architecture and agile development

    Dan Tang received his Ph.D. degree in computer systems organization from the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), Beijing, in 2010. He is currently a senior engineer at the State Key Lab of Processors, ICT, CAS, and the assistant director at the Beijing Institute of Open Source Chip, Beijing. His research interests include computer architecture and low power SoC design

    Sa Wang received his Ph.D. degree in computer science from the Institute of Software, Chinese Academy of Sciences, Beijing, in 2016. He is currently an associate professor at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing. His current research interests include cloud computing and operating systems

    Kan Shi received his Ph.D. degree in digital computing from Imperial College London, in 2015. He is currently an associate professor at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing. His research interests include agile chip design and verification, and custom computing using FPGAs

    Ning-Hui Sun received his Ph.D. degree in computer systems organization from the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), Beijing, in 1999. He is currently a professor at the State Key Lab of Processors, ICT, CAS, Beijing, and an academician of the Chinese Academy of Engineering. His research interests include computer architecture and high-performance computing

    Yun-Gang Bao received his Ph.D. degree in computer systems organization from the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), Beijing, in 2008. He is currently a professor at the State Key Lab of Processors, ICT, CAS, and the deputy director of the ICT, Beijing. His research interests include open source hardware and agile chip design, data center architecture, and memory systems

  • Corresponding author:

    baoyg@ict.ac.cn

  • Received Date: April 06, 2023
  • Accepted Date: July 04, 2023
    Abstract

  • Agile hardware development methodology has been widely adopted over the past decade. Despite the research progress, the industry still doubts its applicability, especially for the functional verification of complicated processor chips. Functional verification commonly employs a simulation-based method of co-simulating the design under test with a reference model and checking the consistency of their outcomes given the same input stimuli. We observe limited collaboration and information exchange through the design and verification processes, dramatically leading to inefficiencies when applying the conventional functional verification workflow to agile development. In this paper, we propose workflow integration with collaborative task delegation and dynamic information exchange as the design principles to effectively address the challenges on functional verification under the agile development model. Based on workflow integration, we enhance the functional verification workflows with a series of novel methodologies and toolchains. The diff-rule based agile verification methodology (DRAV) reduces the overhead of building reference models with runtime execution information from designs under test. We present the RISC-V implementation for DRAV, DiffTest, which adopts information probes to extract internal design behaviors for co-simulation and debugging. It further integrates two plugins, namely XFUZZ for effective test generation guided by design coverage metrics and LightSSS for efficient fault analysis triggered by co-simulation mismatches. We present the integrated workflows for agile hardware development and demonstrate their effectiveness in designing and verifying RISC-V processors with 33 functional bugs found in NutShell. We also illustrate the efficiency of the proposed toolchains with a case study on a functional bug in the L2 cache of XiangShan.

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