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Yin-Shui Xia, Lun-Yao Wang, A. E. A. Almaini. A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock[J]. Journal of Computer Science and Technology, 2005, 20(2).
Citation:
Yin-Shui Xia, Lun-Yao Wang, A. E. A. Almaini. A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock[J]. Journal of Computer Science and Technology, 2005, 20(2).
Yin-Shui Xia, Lun-Yao Wang, A. E. A. Almaini. A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock[J]. Journal of Computer Science and Technology, 2005, 20(2).
Citation:
Yin-Shui Xia, Lun-Yao Wang, A. E. A. Almaini. A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock[J]. Journal of Computer Science and Technology, 2005, 20(2).
A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock
A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. Pspice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.
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