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Wei-Wu Hu, Xue-Jun Yang, Xiao-Wei Li. Preface. Journal of Computer Science and Technology, 2010, 25(2): 179-180.
Citation: Wei-Wu Hu, Xue-Jun Yang, Xiao-Wei Li. Preface. Journal of Computer Science and Technology, 2010, 25(2): 179-180.
  • CPU is the "heart'' of information systems. As the key technology of IT industry, it increasingly plays an important role in national economy and information security. We are pleased to present this selection of nine papers in this Special Section on CPU Researches in China. The authors are from leading universities and research institutions. The achievements presented in these papers have been supported by the projects from NSFC, 863, 973 etc. We believe that this collection represents the state-of-the-art progresses in the field of microprocessor research and development in China.

    The paper "System Architecture of Godson-3 Multi-Core Processors'' by Xiang Gao et al. introduces the system architecture of Godson-3 from aspects including system scalability, organization of memory hierarchy, network on-chip, inter-chip connection and I/O subsystem.

    The paper "Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor'' by Bao-Xia Fan et al. describes the design methodology of the physical implementation of Godson-3A, with particular emphasis on design flow, design methods for high frequency, clock tree design, power management, and on chip variation issue.

    The paper "Research Progress of UniCore CPUs and PKUnity SoCs'' by Xu Cheng et al. reviews the evolution of the UniCore CPU and the PKUnity SoC family, and introduces the hardware/software co-design platform.

    The paper "YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP'' by Shu-Ming Chen et al. presents a novel heterogeneous multi-core architecture DSP processor, and provides a simple parallel programming environment.

    The paper "Physical Design Methodology for Godson-2G Microprocessor'' by Ji-Ye Zhao et al. proposes the design flow of Godson-2G microprocessor, and provides three physical design methodologies, an interconnect-centric driven floorplan generation, auto-adapted boundary constraints design optimization, and automatic register group clock tree generation.

    The paper "Managing Data-Objects in Dynamically Reconfigurable Caches'' by Xue-Jun Yang et al. proposes a quantitative framework for analyzing the cache requirement of data-objects, which includes cache capacity, block size, associativity and coherence protocol.

    The paper "Hierarchical Cache Directory for CMP'' by Song-Liu Guo et al. introduces hierarchical cache directory into CMP, which divides CMP tiles into multiple regions hierarchically, and combines it with data replication, and proposes a new directory organization to record the share status within a region and assist the regional home to complete operation efficiently.

    The paper "CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors'' by Jing-Lei Wang et al. proposes cache coherent network on chip, a scheme that decouples cache coherency maintenance from processors and shared L2 caches and implements it completely in network on chip to free up processors and shared L2 caches from the chore of maintaining coherency.

    The paper "Design and Application of Instruction Set Simulator on Multi-Core Verification'' by Xiang-Dong Hu et al. proposes a general methodology to expand a single-core instruction set simulator (ISS) to a multi-core ISS.

    The guest editors hope that the technological developments and empirical findings as presented in this special section will help encourage the research on the related fields. We would like to thank all the referees who have worked hard to review each paper and provided authors with constructive comments. We sincerely hope that the readers will enjoy reading this special section.
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