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Farid Mheir-ELSaadi, Bozena Kaminska. An Automatic Hierarchical Delay Analysis Tool. Journal of Computer Science and Technology, 1994, 9(4): 349-364.
Citation: Farid Mheir-ELSaadi, Bozena Kaminska. An Automatic Hierarchical Delay Analysis Tool. Journal of Computer Science and Technology, 1994, 9(4): 349-364.

An Automatic Hierarchical Delay Analysis Tool

  • The performance analysis of VLSI integrated circuits (ICs) with llat tools is slow and even sometimes impossible to complete. Some hierarchical tools have been developed to speed up the analysis of these large ICs. However, these hierarchical tools suffe from a poor interaction with the CAD database and poorly automatized operations. We introduce a general hierarchical framework for performance analysis to solve these problems. The circuit analysis is automatic under the proposed framework. Information that…
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