A Logic Design Automation System for Generating Logic Diagram from Hardware Description

This paper discusses a logic design automation system (LODAS) implemented on APOLLO DOMAIN workstation. LODAS can generate VLSI logic diagram from the hardware description. The system accepts many kinds of input description such as DDL or AHPL language description, functional array (truth table), covering array, Boolean equations or state transition tables. The system first simulates the functional description to verify the functional description of the system designed, then the translator translates the functional description into register transfer equations, Boolean equations and state transition equations automatically. Logic synthesis software partitions the translation result into a series of blocks, and transforms every small block into a multi-level NAND/NOR network according to the fan-in and fan-out restriction.