IDDT: Fundamentals and Test Generation

It is the time to explore thefundamentals of DDT testing when extensive work has been donefor DDT testing since it was proposed. This paper preciselydefines the concept of average transient current DDT ofCMOS digital ICs, and experimentally analyzes the feasibility of DDT test generation at gate level. Based on the SPICE simulationresults, the paper suggests a formula to calculate DDT bymeans of counting only logical up-transitions, which enables DDTtest generation at logic level. The Bayesian optimizationalgorithm is utilized for DDT test generation. Experimentalresults show that about 25% stuck-open faults are with DDTtestability larger than 2.5, and likely to be DDT testable. Itis also found that most DDT testable faults are located nearthe primary inputs of a circuit under test. DDT testgeneration does not require fault sensitization procedure compared withstuck-at fault test generation. Furthermore, some redundant stuck-atfaults can be detected by using DDT testing.