A Novel RT-Level Behavioral Description Based ATPG Method

The paper proposes a novel ATPG(Automatic Test Pattern Generation) method based on RTL (RegisterTransfer Level)behavioral descriptions in HDL (Hardware Description Language). Themethod is simulation-based. Firstly, itabstracts RTL behavioral descriptions to Process Controlling Trees (PCT)and Data Dependency Graphs (DDG), which are used for behavioralsimulation and data tracing. Transfer faults are extracted from DDGedges, which compose a fault set needed for test generation. Then,simulation begins without specifying inputs in advance, and arequest-echo strategy is used to fix some uncertain inputs if necessary.Finally, when the simulation ends, the partially fixed input sequence isthe generated test sequence. The proposed request-echo strategy greatlyreduces unnecessary backtracking, and always tries to cover uncoveredtransfer faults. Therefore, the proposed method is very efficient, andgenerates tests with good quality. Experimental results demonstrate thatthe proposed method is better than ARTIST in three aspects: (1) the CPUtime is shorter by three orders of magnitude; (2) the test length isshorter by 52%; and (3) the fault coverage is higher by 0.89%.