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Ashish Pancholy, Fidel Muradali, Vinod K.Agarwal. A Hierarchical Reconfiguration Strategy for Bus-Based Multiprocessors[J]. Journal of Computer Science and Technology, 1990, 5(2): 175-186.
Citation: Ashish Pancholy, Fidel Muradali, Vinod K.Agarwal. A Hierarchical Reconfiguration Strategy for Bus-Based Multiprocessors[J]. Journal of Computer Science and Technology, 1990, 5(2): 175-186.

A Hierarchical Reconfiguration Strategy for Bus-Based Multiprocessors

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  • Published Date: April 09, 1990
  • A method of providing redundancy to a class of bus-based multiprocessor arrays is discussed.The reconfiguration is hierarchical,providing global spare replacement at the array level and local reconfiguration within the spare block.Results of yield analysis performed on a 32 processor array are pres- ented.
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    T.E.Mangir, Sources of Failures and Yield Improvements for VLSI, IEEE Proceedings, 72:6(1984).
    [2]
    A.L.Rosenberg, The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors, IEEE Trans.on Comput., C-32 (1983).
    [3]
    A.S.M.Hassan and V.K.Agarwah, A modular approach to fault-tolerant binary tree architectures. FTCS-15 Proceedings,344-349,1985.
    [4]
    Henry Cox et al., Design of a Massively Parallel Processor with Soft Reconfiguration, McGill University VLSI Lab Report No.88-3R, March 1988.
    [5]
    Jim Harden and Noel Strader II, Architectural Yield Optimization for WSI, IEEE Trans. on Comput.,C-37:1 (1988).
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