Building compiler backends by producing the *.td files for a new target manually as in (a) prior work and automatically as in (b) this work.

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Building compiler backends by producing the *.td files for a new target manually as in (a) prior work and automatically as in (b) this work.

2023, 38(6): 1339-1355.

Automatic Target Description File Generation .

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Heavy research and development (R&D) efforts in writing target description (.td) files for a new target in LLVM 12.0.
Reduced R&D efforts in specifying a few target-specific properties.
Building compiler backends by producing the *.td files for a new target manually as in (a) prior work and automatically as in (b) this work.
Motivating example for illustrating ATG. (a) Bit encoding of c.jr from RISC-V. (b) Hand-written description of c.jr taken from LLVM. (c) Description of c.jr generated by ATG automatically. (d) The only effort from compiler developers for c.jr. (e) Example records (MicroMIPS and MIPS64). (f) TRGs (MicroMIPS and MIPS64). (g) ISA models (MicroMIPS and MIPS64). (h) Target-specific property list. (i) Synthesized code-layout template list. (j) Synthesized TPLRec-List for c.jr. (k) Target-specific properity list (TSP-List). (l) Similarity-based matching. (m) Schemes for failed matching. Ri: record i. Idx: index.
Framework of Automatic Target Description File Generation (ATG).
Target-specific properties distribution among different ISAs.
Code-layout template for failed match instructions. (a) Bit encoding of c.fldsp from RISC-V. (b) Hand-written description of c.fldsp taken from LLVM. (c) Automatically generated description of c.fldsp by ATG. (d) Only effort by developers for c.fldsp. (e) Target-specific properity list (TSP-List). (f) Auxiliary template (AUX-TPL) for failed match instructions.
Experiments on instruction generation with LLVM regression tests. (a) RV32-mode. (b) RV64-mode.

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