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Volume 25 Issue 2
March  2010
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Xiang-Dong Hu, Yong Guo, Ying Zhu, Xin Guo, Peng Wang. Design and Application of Instruction Set Simulator on Multi-Core Verification[J]. Journal of Computer Science and Technology, 2010, 25(2): 267-273.
Citation: Xiang-Dong Hu, Yong Guo, Ying Zhu, Xin Guo, Peng Wang. Design and Application of Instruction Set Simulator on Multi-Core Verification[J]. Journal of Computer Science and Technology, 2010, 25(2): 267-273.
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Design and Application of Instruction Set Simulator on Multi-Core Verification

  • National High Performance IC (Shanghai) Design Center, Shanghai 201204, China

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  • Author Bio:

    Xiang-Dong Hu is a processor in National High Performance IC(Shanghai) Design Center. He is a senior member of ChinaComputer Federation (CCF). He received his B.S. and M.S. degrees inelectrical engineering from Zhejiang University. His main researchinterests include high performance computer architecture, and highperformance processor design & verification.

    Yong Guo is an assistant processor in National High Performance IC(Shanghai) Design Center. His research interests include simulation,verification, and compiler optimization.

    Ying Zhu is a processor in National High Performance IC (Shanghai) DesignCenter. Her research interests include high performance processor design& verification, and hardware design.

    Xin Guo is an associate processor in National High Performance IC(Shanghai) Design Center. Her research interests include high performanceprocessor design, and hardware design.

    Peng Wang is an assistant processor in National High Performance IC(Shanghai) Design Center. He received the Ph.D. degree from TsinghuaUniversity. His research interests include high performance processor design.

  • Received Date: March 22, 2009
  • Revised Date: January 24, 2010
  • Published Date: March 04, 2010
    Abstract
  • Instruction Set Simulator (ISS) is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi-core ISS (MCISS) is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the ``save and restore'' mechanism, the verification procedure and the debugging are speeding up greatly.
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    • References (14)
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