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Volume 11 Issue 6
November  1996
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Yan Zongfu, Liu Mingye. The RTL Binding and Mapping Approach of VHDL High-Level Synthesis System HLS/BIT[J]. Journal of Computer Science and Technology, 1996, 11(6): 562-569.
Citation: Yan Zongfu, Liu Mingye. The RTL Binding and Mapping Approach of VHDL High-Level Synthesis System HLS/BIT[J]. Journal of Computer Science and Technology, 1996, 11(6): 562-569.
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The RTL Binding and Mapping Approach of VHDL High-Level Synthesis System HLS/BIT

  • Department of Computer Science & Engineering Beijing Institute of Technology; Beijing 100081;

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  • Published Date: November 09, 1996
    Abstract
  • This paper describes a VHDL high-level synthesis system HLS/BIT with emphasis on its register-transfer level (RTL) binding and technology mapping subsystem. In more detail, the component instantiation mechanism and the knowledge-driven approach to RTL technology mapping are also presented.
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    • References (3)
  • [1]
    Liu Mingye. Guo Shuming. Intelligent problems of design automation system. Journal of Computer Aided Design & Graphics, 1989, 1(2): 66-72.
    [2]
    Chen Gwodong, Gajski.D.D. An intelligent component database for behavioral synthesis. In Proc. of ,7th DAC 1990, pp.150-155.
    [3]
    Nikil.D.Dutt, James.R.Kipps. Bridging high-level synthesis to RTL technology libraries. In Proc. of ,8th DAC, 1991, pp.526-529. ……….
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