Overall architecture of the proposed accelerator. SPE: scalar processing element.

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Overall architecture of the proposed accelerator. SPE: scalar processing element.

2023, 38(6): 1300-1322.

Hardware Acceleration for SLAM in Mobile Systems .

Figures of the Article

Overall flow of EKF/PF SLAM.
Overall flow of RGB-D SLAM^[18].
Overall flow of ORB SLAM^[32].
Analysis of performance and power bottlenecks. (a) Breakdown of execution time of different stages. (b) Breakdown of power of different stages.
CPI stack of BenchSLAM.
CPI stack of BenchSLAM comparison among branch misprediction of SPEC CPU 2006 benchmarks (gcc and libquantum), neural network algorithms (CNN Train and CNN Test), and BenchSLAM algorithms (EKF, PF, RGB-D SIFT, RGB-D SURF, and ORB).
Overall architecture of the proposed accelerator. SPE: scalar processing element.
Architecture of the matrix processing unit (MPU), which consists of an array of $P_{x} \times P_{y}$ matrix processing elements (MPEs) and a buffer controller. (a) MPU architecture. (b) MPE architecture.
Architecture of a vector processing unit (VPU), which consists of $P_{z}$ vector processing elements (VPEs). (a) VPU architecture. (b) VPE architecture.
Architecture of the control unit (CU). Inst.: instruction.
CONV on MPU (using ${3\times 3}$ MPU in the example). (a) Scheduling of CONV instruction. (b) Data reuse between MPEs (four MPEs in the example).
Convolution code using non-macro instructions.
MMmV: the matrix-vector multiplication on MPU. ${*}$ means the multiplication operation.
MMmM: the matrix-matrix multiplication on MPU.
MVmV: the vector-vector multiplication on MPU. (a) Multiplication of $P_{x} \times P_{y}$ pairs of inputs. (b) Accumulated partial productions in each MPE ( $P_{x} \times P_{y}$ MPEs in total). (c) Propagating accumulation-summation from right to left in each MPE row. (d) Propagating accumulation-summation (Acc-Sum) from bottom to top in the left-most MPE column and outputting the final result from the top-left-most MPE.
VVmV: the vector-vector multiplication on VPU. (a) Multiplication of $P_{z}$ pairs of inputs. (b) Accumulated partial productions in each VPE ( $P_{z}$ VPEs in total). (c) Propagating accumulation-summation from right to left and outputting the final result from the left-most VPE.
Mapping process of the SIFT algorithm. : subtraction.
Mapping process of the g²o algorithm. b: coefficient vector. $\varDelta x$ : increments of pose. $\boldsymbol b=\boldsymbol H\cdot \varDelta x$ .
Layout of the implemented accelerator (45 nm).
Accelerator (Acc) and x86 CPU (x86) speedups over ARM CPU on BenchSLAM.
Energy costs of CPUs (x86 and ARM) and accelerator (Acc) on BenchSLAM.

Others

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